The present invention relates to a method for producing three-dimensional circuits and especially three-dimensional integrated circuits.
Three-dimensional integration means the vertical connection of components which have been produced by means of planar technology. The advantages of a three-dimensional integrated microelectronic system are e.g. that, in comparison with two-dimensional systems, higher packaging densities and switching speeds can be achieved observing the same design rules. The latter is, on the one hand, due to shorter line paths between the individual components or circuits, and, on the other hand, it is due to the possibility of parallel data processing. The increase in the performance of the system will be optimal when a connection technology with locally freely selectable VLSI vertical contacts is realized.
For producing three-dimensional circuit arrangements with freely selectable vertical contacts, the following methods are already known:
Y. Akasaka, Proc. IEEE 74 (1986) 1703, suggests that polycrystalline silicon should be deposited on a fully processed layer of components and recrystallized so that further components can be produced in the recrystallized layer. Disadvantages of this method are the yield-reducing degradation of the components in the lower plane caused by the high thermal load occurring during the recrystallization process and the necessarily serial processing of the complete system. The latter causes, on the one hand, long processing times in the production process and, on the other hand, it results in a yield reduction due to a summation of the process-conditioned rejects. Both factors will substantially increase the production costs in comparison with processing of the individual planes separately from one another in different substrates.
Y. Hayashi et al Proc., 8th Int. Workshop on Future Electron Devices, 1990, p. 85, discloses that the individual component planes are first produced separately from one another in different substrates. Subsequently, the substrates are thinned to a thickness of a few millimeters, provided with contacts on the front and on the back and vertically connected by means of a bonding process. For providing the contacts on the back and on the front, special processes are, however, necessary which are not part of the standard semiconductor production technology (CMOS), viz. MOS-incompatible materials (e.g. gold) and the structuring of the back of the substrate.
U.S. Pat. No. 4,939,568 describes a method of producing a three-dimensional integrated circuit structure by stacking individual integrated circuits (ICs=integrated circuits) so as to form a stack of individual chips on a support substrate. For this purpose, a substrate with fully processed ICs is first divided into individual chips, whereby processing at the wafer level is finished. The chips are tested and a first individual chip is applied to a support substrate by means of thermocompression. After this step, a further chip is applied to the first chip in the same way. Hence, a first stack of chips is finished before the production of a further stack of chips on another support substrate is started. It follows that further processing of the stacks of chips at the wafer level is not possible by means of this method.
A substantial disadvantage of the above-described methods originates from the fact that the devices available in the field of silicon technology only permit processing of disk-shaped substrates, the so-called wafers. A processing of non-disk-shaped substrates, in particular of individual chips, is only possible in experimental plants, but not within the framework of an industrial production with the high yields demanded.
U.S. Pat. No. 4,954,875 describes a method for three-dimensional integration by stacking individual wafers in the case of which the connection of the individual component planes is established through specially shaped vias (through-holes). When substrates comprising a large number of identical components, the so-called chips, are combined, the resultant yield of a multilayer system results from the product of the individual yields. This has the effect that the yield of a system comprising a plurality of component planes, like the system disclosed in U.S. Pat. No. 4,954,875, decreases drastically according to the known methods. When the yield of an individual plane is, for example, 80%, the resultant total yield in the case of a complete system of 10 planes will only be approx. 10%, which means that such a system is no longer economical and that the use of this technology is limited to a few special fields of application. The yield of a component substrate also depends on the kind of circuits and on the production process used. The yields achieved in the production of storage components are, for example, very high, whereas the yield achieved in the case of logic chips, such as microprocessors, is markedly lower. In particular when several kinds of such circuits are stacked one on top of the other, the total yield is determined by the lowest-yield circuit type to a disproportionate degree.
U.S. Pat. No. 5,563,084 describes a method for producing a three-dimensional integrated circuit; making use of the conventional standard industrial equipment, this method achieves at the wafer level a substantial increase in yield in comparison with the yield of hitherto described methods. According to this method, two fully processed substrates are connected. The upper substrate is, however, previously subjected to a function test with the aid of which the intact chips of the substrate are selected. Subsequently, this substrate is thinned from the back, divided into individual chips and only selected, intact chips are applied in a juxtaposed, aligned mode of arrangement to the lower substrate which is provided with an adhesive layer. Due to the fact that only selected chips are applied, an increase in yield is achieved, but in the case of a defective sub-system intact chips are still applied and thus wasted, and this will entail unnecessary costs.
It is the object of the present invention to provide a method for producing a three-dimensional integrated circuit, which is improved in comparison with the above-described method and by means of which a high system yield is achieved at the wafer level making use of a conventional standard industrial equipment, the costs being low in comparison with the costs entailed by hitherto known methods.
This object is achieved by a method for producing three-dimensional circuits comprising the following steps: providing a first substrate and a second substrate, each of said substrates having arranged therein a plurality of components which have been tested with regard to their operability; dicing the second substrate so as to obtain a plurality of individual chips, each individual chip comprising at least one component; arranging the individual chips on the first substrate and connecting them to said first substrate so that operative components in said first substrate are connected to individual chips comprising an operative component, and so that non-operative components in said first substrate are connected to chip elements having no function, so as to obtain a three-dimensional complete structure; and dicing the three-dimensional complete structure so as to obtain three-dimensional circuits.
The present invention provides a method for producing three-dimensional circuits in the case of which a first and a second substrate are first provided, each of these substrates having arranged therein a plurality of components which have been tested with regard to their operability. Subsequently, the second substrate is diced so as to obtain a plurality of individual chips, each individual chip comprising at least one component. Following this, the individual chips are arranged on the first substrate and connected to the first substrate so that operative components in the first substrate are connected to individual chips comprising an operative component, and so that non-operative components in the first substrate are connected to chip elements having no function, so as to obtain a three-dimensional complete structure. Finally, the three-dimensional complete structure is diced so as to obtain the three-dimensional circuits.
According to a preferred embodiment, the step of providing the first and the second substrate comprises the production of the first substrate by processing a first semiconductor wafer so as to form a plurality of components therein and by forming a metallization structure for contacting the components, the testing of the plurality of components in the first substrate with regard to their operability so as to be able to differentiate between operative components and non-operative components, the production of the second substrate by processing a second semiconductor wafer so as to form the plurality of components therein and by forming a metallization structure, and the subsequent testing of the plurality of components in the second substrate with regard to their operability so as to be able to differentiate between operative individual chips and non-operative individual chips.
According to a further preferred embodiment, the chips used as chip elements having no function are the non-operative individual chips which are connected to non-operative components in the first substrate.
According to a further preferred embodiment, the first substrate may, in turn, already comprise a plurality of component layers in the form of stacks of components, and also the second substrate can have applied thereto further component planes in a chipwise mode of application after the application of the individual chips and before the dicing of the complete structure.
In total, the method according to the present invention uses known and accepted method steps so that, according to a special advantage of the present invention, it is not necessary to develop any new processes. One advantage of the present invention is to be seen in the fact that processing at the wafer level remains possible.
By means of the method according to the present invention only intact chips are applied to respective intact chips of the underlying component layers, whereas defective chips of the underlying component layers have applied thereto chips which are also defective. This means that the dependence of the yield of the complete system on the yield of the individual processed substrates is markedly reduced in an advantageous manner. It is possible to eliminate only individual defective chips of a component layer so that a single defective layer will no longer spoil whole stacks of components. It follows that the method according to the present invention will markedly increase the yield in the production of three-dimensional integrated circuits and it will reduce the production costs simultaneously.